1. Field of the Invention
The present invention relates to a placement and routing method for a semiconductor device, and more specifically to a placement and routing method for a semiconductor integrated circuit, using a computer aided design (abbreviated to a xe2x80x9cCADxe2x80x9d).
2. Description of Related Art
At the time of performing a layout design by use of the CAD, the design is performed for each of different kinds of basic cells including an inverter, NAND, NOR, etc. In this case, it is general that in the same basic cell, a plurality of transistors constituting the basic cell are different in transistor size from one another, because of a circuit characteristics of an individual basic cell. In the prior art, therefore, a design method has been adopted in which a required number of kinds of basic cells, namely, parameterized cells are previously prepared in order to automatically generate necessary basic cells when a design rule, a transistor size and others are inputted.
The prior art placement and routing method for realizing the above mentioned parameterized cells includes the following two approaches: Namely, a first placement and routing method is that only transistors are expressed as an object, and wiring conductors and contacts are described by a relational equation; and a second placement and routing method is that transistors are described as an object, and only a relative position between transistor objects are designated, and a wiring between the objects is automatically performed in accordance with connection information.
Firstly, a concept of the transistor object will be explained with reference to FIG. 1 which diagrammatically illustrates the transistor object. The transistor object is expressed by expressing a transistor graphic form as one set regardless of the transistor size, and includes imaginary terminal positions TG, TS and TD of a gate, a source and a drain, transistors sizes L (length) and W (width), and a location origin position OXY.
Now, the first prior art placement and routing method will be explained with reference to a flow chart of FIG. 2. First, in a step P1, parameters of the transistor size are set as the transistor object, and then, a relational equation between the transistor object and wiring conductors and contacts is described. This relational equation is prepared to the effect that a location position or a wiring position is determined on the basis of already located graphic forms and the design rule. Furthermore, the wiring description includes information concerning a designated wiring conductor layer, and the contact description includes a name of a contact cell to be located.
In a step P2, the origin of a first transistor object is determined, and in accordance with the relational equation, generation and location of transistors in a step P4, or a location of wiring conductors in a step P5 and a location of contacts in step P6 are performed. In a step P3, whether or not the location object is the transistor object is checked, and if the location object is the transistor object, the processing goes into the step P4 in which the transistor is generated in accordance with given parameters, and a location position of the generated transistor is determined on the basis of the relational equation. On the other hand, if the location object is the wiring conductors, the processing goes into the step P5 in which a starting point and a terminating point of the wiring conductor are calculated in accordance with the relational equation, and the wiring is performed by using the designated wiring conductor layer. Furthermore, if the location object is the contact, the processing goes into the step P6 in which the location position is calculated in accordance with the relational equation, and a designated contact cell is located. This processing is performed for all the contents describing the relational equations.
Now, a specific example of this processing will be described with reference to FIG. 3A showing a layout diagram of cells to be located and wired and FIG. 3B illustrating the same by the relational equation of the transistor objects. Transistors Q1 and Q2 shown in FIG. 3A are expressed by transistor objects QO1 and QO2 shown in FIG. 3B, respectively. Wiring conductors W1, W2, W3, W4 and W5 shown in FIG. 3A are expressed by wiring conductors WO1, WO2, WO3, WO4 and WO5 shown in FIG. 3B, respectively, which indicate a center line of the path. Contacts TH1 and TH2 shown in FIG. 3A are expressed by contacts THO1 and THO2 shown in FIG. 3B, respectively.
For example, in the case of locating the wiring conductor WO2, it is necessary to determine end points P21 and P22. If the transistor object QO1 is located, an X-coordinates of the end point P21 is positioned at a position for separating the wiring conductor WO1 from the transistor object QO1 by a spacing interval of the design rule, and a Y-coordinates of the end point P22 is positioned at a position for separating the wiring conductor WO2 from the transistor object QO1 by the spacing of the design rule. A Y-coordinates of the end point P21 is the same as a Y-coordinates of the end point P22, and an X-coordinates of the end point P22 is the same as an X-coordinates of the terminal T26 of the transistor object QO2.
Therefore, the X-coordinates and the Y-coordinates of the end point P22 are obtained after processing the wiring conductor WO4, the contact TH2 and the transistor object QO2 and deciding the terminal T26 of the transistor object QO2. Finally, the end points P21 and P22 are interconnected by a designated wiring conductor layer and a designated wiring conductor width.
In this first prior art placement and routing method, in the case of determining the wiring conductor WO2, it is necessary to consider the position of the terminal of the transistor object QO2 which is not directly connected to the wiring conductor WO2. In other words, as regards a wiring conductor which is not directly connected to the terminal of the transistor object, it is necessary to investigate influence of all the terminal positions, and to determine the wiring order and the location order of the transistor objects, if necessary, in order to introduce them into the relational equation. This makes the relational equation complicated, and becomes easy to overlook the wiring conductor subjected to influence, when the number of transistors is large.
Furthermore, in order to realize the first prior art placement and routing method, it is a general practice to describe a cell generation program for each cell, and therefore, it is not possible to hold data per each cell, and therefore, it is difficult to modify a cell constituting element.
Now, the second prior art placement and routing method will be explained with reference to a flow chart of FIG. 4. First, in a step R1, parameters of the transistor sizes are set as the transistor object, and then, a relative position between the transistor objects is designated. Then, in a step R2, transistors is generated in accordance with the parameters of the transistor described in the relative position information. Thereafter, in a step R3, a location position (origin) of a first transistor object is determined, and in a step R4, the generated transistors are located in accordance with the relative position described in the relative position information. At this time, adjustment is conducted to avoid the transistors from being overlapped to one another. Then, in a step R5, a wiring is conducted to connect between the located transistors by use of diffused layers, polysilicon wiring layers, and aluminum wiring layers, in accordance with the connection information.
This wiring is conducted by first communizing the transistors by using the diffused layers, and then, by making the connection by use of the polysilicon wiring layers and the aluminum wiring layers. At this time, when it becomes necessary to connect the wiring layers of different levels, a necessary contact is located to satisfy the design rule. Alternatively, if a space required for the wiring conductor does not exist between the transistors, a processing is conducted to expand the spacing between the transistors.
Now, a specific example of this processing will be described with reference to FIG. 5A showing a layout diagram of cells to be located and wired and FIG. 5B illustrating a relative position of the cells by the relational equation of the transistor objects. Transistors Q3, Q4 and Q5 shown in FIG. 5A are expressed by transistor objects QO3, QO4 and QO5 shown in FIG. 5B, respectively, which show a relative position of these transistors.
First, transistors are generated in accordance with the sizes L and W of the respective transistor objects QO3, QO4 and QO5, and the generated transistors are located in such a manner that the transistors never overlap with one another. Then, in accordance with the connection information, the diffused layers of the transistor objects QO3, QO4 and QO5 are communized to a possible extent, and further, connections between terminals of the transistors are performed by use of the polysilicon wiring layers and the aluminum wiring layers. At this time, when the wiring layers to be connected to each other are at different levels, a connection contact is located.
If a wiring space is insufficient at the stage of generating wiring conductors W15 and W14 and contacts TH3 and TH4, a spacing between the transistor object QO5 and the transistor objects QO3 and QO4 is expanded to a necessary degree. Ultimately, a layout as shown in FIG. 5A is obtained.
In this second prior art location and routine method, however, for example when the channel length L of the transistor Q5 is enlarged, there is possibility that the wiring conductors W14 and W13 are generated to take a roundabout or circuitous route avoiding the transistors Q3 and Q4, as a wiring pattern indicated by wiring conductors W14A and W13A, W13B and W13C and contacts TH23 and TH24 shown in FIG. 5C, with the result that there is generated the necessity of interconnecting the wiring conductors of different levels. This is considered to be generated in the course of calculating the cost of the wiring route in an automatic wiring processing. If the circuitous route wiring conductor is generated, the circuit area becomes large, and an extra wiring capacitance is added. Furthermore, in order to realize the second prior art location and routing method, a large scaled automatic wiring tool and a so called compaction program become necessary.
As mentioned above, the first prior art location and routing method is disadvantageous in that it is necessary to investigate influence of terminal positions of transistor objects for all wiring conductors including wiring conductors which are not connected directly to the terminals of the transistor objects, and to determine the wiring order and the location order of the transistor objects, if necessary, in order to introduce them into the relational equation. Therefore, when the number of transistors is large, the relational equation becomes complicated, and it becomes easy to overlook the wiring conductor subjected to influence.
Furthermore, it is necessary to describe a cell generation program for each cell, and therefore, it is not possible to hold inherent data per each cell. As a result, it is difficult to modify a cell constituting element, for example to change the size of some transistors.
On the other hand, the second prior art location and routing method is disadvantageous in that, because of the automatic wiring, when the transistor size is changed, there is possibility of generation of a circuitous route wiring which increases the circuit area and the wiring capacitance.
Furthermore, in order to realize the second prior art location and routing method, a large scaled automatic wiring tool and a so called compaction program become necessary.
Accordingly, it is an object of the present invention to provide a placement and routing method for a semiconductor integrated circuit, which has overcome the above mentioned defects of the conventional ones.
Another object of the present invention is to provide a placement and routing method for a semiconductor integrated circuit, capable of reducing the number of layout design steps while holding the relative position of constituents.
The above and other objects of the present invention are achieved in accordance with the present invention by a placement and routing method for the semiconductor integrated circuit having circuit elements or function circuit blocks, including transistors, on a semiconductor chip, the placement and routing method being for automatically generating necessary parameterized cells by giving a design rule and a design information including the size of the transistors, the method including:
an object describing step for preparing an object description which describes each of the transistors as a transistor object and each wiring conductor as a wiring object, and which includes a relative position information of each object in relation to an adjacent object and a connection information indicative of a connection destination of each object:
a transistor object processing step for generating the transistors in accordance with the object description and locating the generated transistors by considering the relative position information;
a wiring object processing step for determining a position of the each wiring object in a horizontal direction and in a vertical direction by considering the relative position information;
an object end point determining step for determining a final position of each transistor object and a final staring point and a final terminating point of each wiring object; and
a wiring post-processing step for wiring each wiring object by a designated wiring layer.